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Raspberry Pi /RP2350 /OTP_DATA_RAW /CRIT1

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Interpret as CRIT1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SECURE_BOOT_ENABLE)SECURE_BOOT_ENABLE 0 (SECURE_DEBUG_DISABLE)SECURE_DEBUG_DISABLE 0 (DEBUG_DISABLE)DEBUG_DISABLE 0 (BOOT_ARCH)BOOT_ARCH 0 (GLITCH_DETECTOR_ENABLE)GLITCH_DETECTOR_ENABLE 0GLITCH_DETECTOR_SENS

Description

Page 1 critical boot flags (RBIT-8)

Fields

SECURE_BOOT_ENABLE

Enable boot signature enforcement, and permanently disable the RISC-V cores.
SECURE_DEBUG_DISABLE

Disable Secure debug access
DEBUG_DISABLE

Disable all debug access
BOOT_ARCH

Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set.
GLITCH_DETECTOR_ENABLE

Arm the glitch detectors to reset the system if an abnormal clock/power event is observed.
GLITCH_DETECTOR_SENS

Increase the sensitivity of the glitch detectors from their default.

Links

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Register License

Copyright © 2024 Raspberry Pi Ltd.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data